/*========================================================

----------------------------------------------------------

	Pulse & Pattern Generator

	                                S.Ishijima 2002.04.07
----------------------------------------------------------




          +--------------------------> clk_50n
          |
    clk---+--> clk_div10_1 --+-------> clk_500n
                             |
          +------------------+
		  |
		  +--> clk_div10_2 --+-------> clk_5u
                             |
          +------------------+
		  |
		  +--> clk_div10_3 --+-------> clk_50u
                             |
          +------------------+
		  |
		  +--> clk_div10_4 --+-------> clk_500u
                             |
          +------------------+
		  |
		  +--> clk_div10_5 --+-------> clk_5m
                             |
          +------------------+
		  |
		  +--> clk_div10_6 --+-------> clk_50m
                             |
          +------------------+
		  |
		  +--> clk_div10_7 --+-------> clk_500m



                      rangesel
                  +--------------+
	clk_50n  ---->|d0            |
	clk_500n ---->|d1            |
	clk_5u   ---->|d2            |
	clk_50u  ---->|d3    mux8    |----> div_clk1
	clk_500u ---->|d4            |	
	clk_5m   ---->|d5            |
	clk_50m  ---->|d6            |
	clk_500m ---->|d7            |
                  +--------------+
                         ^
		                 |
						 range_sw


	div_clk1--+--> [clk_div2] -----> div_clk2
              |
			  +--> [clk_div5] -----> div_clk5




                      divsel
                  +--------------+
	div_clk1 ---->|d0            |
	div_clk2 ---->|d1  mux4      |----> div_clk
	div_clk5 ---->|d2            |
	  GND    ---->|d3            |
                  +--------------+
                         ^
		                 |
						 div_sw



	preset_sw | (div_sw[0] & div_sw[1]) ----> preset


                  +-----------------+
	div_clk  ---->|         clk_divp|---->pck_out 
	              |         clk_divn|---->nck_out
	preset    --->|                 |
                  +-----------------+
                        clk_div2pn


                  +-----------------+
	div_clk  ---->|   counter3      | ====> clk_count
    reset_sw ---->|                 |
                  +-----------------+


					pata_sel
                  +--------------+
 	pata_sw[0]--->|d0            |
 	pata_sw[1]--->|d1            |
 	pata_sw[2]--->|d2            |
 	pata_sw[3]--->|d3  mux8      |----> pata
 	pata_sw[4]--->|d4            |
 	pata_sw[5]--->|d5            |
 	pata_sw[6]--->|d6            |
 	pata_sw[7]--->|d7            |
                  +--------------+
                         ^
		                 |
						 clk_count


					 pata_ff
                  +-----------------+
	pata     ---->|d    dff        q|---=> dpata
    reset_sw ---->|rst              |
    div_clk  ---->|clk              |
                  +-----------------+




					patb_sel
                  +--------------+
 	patb_sw[0]--->|d0            |
 	patb_sw[1]--->|d1            |
 	patb_sw[2]--->|d2            |
 	patb_sw[3]--->|d3  mux8      |----> patb
 	patb_sw[4]--->|d4            |
 	patb_sw[5]--->|d5            |
 	patb_sw[6]--->|d6            |
 	patb_sw[7]--->|d7            |
                  +--------------+
                         ^
		                 |
						 clk_count


					 patb_ff
                  +-----------------+
	patb     ---->|d    dff        q|---=> dpatb
    reset_sw ---->|rst              |
                  +-----------------+


	dpata 	---> inv ---> n_pata
	dpatb 	---> inv ---> n_pata
	nck_out	---> inv ---> n_nck_out
	pck_out	---> inv ---> n_pck_out



%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Fitting Constraints        for XC9572PC44
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%


NET "patb_sw<3>" LOC = "P36";
NET "patb_sw<2>" LOC = "P37";
NET "patb_sw<1>" LOC = "P38";
NET "patb_sw<0>" LOC = "P40";
NET "div_sw<0>" LOC = "P14";
NET "div_sw<1>" LOC = "P13";
NET "clk" LOC = "P6";
NET "range_sw<2>" LOC = "P12";
NET "range_sw<1>" LOC = "P7";
NET "range_sw<0>" LOC = "P9";
NET "pata_sw<7>" LOC = "P42";
NET "pata_sw<6>" LOC = "P43";
NET "pata_sw<5>" LOC = "P44";
NET "pata_sw<4>" LOC = "P1";
NET "pata_sw<3>" LOC = "P2";
NET "pata_sw<2>" LOC = "P3";
NET "pata_sw<1>" LOC = "P4";
NET "pata_sw<0>" LOC = "P5";
NET "n_pck_out" LOC = "P28";
NET "n_nck_out" LOC = "P26";
NET "n_pata" LOC = "P24";
NET "n_patb" LOC = "P22";
NET "patb_sw<7>" LOC = "P29";
NET "patb_sw<6>" LOC = "P33";
NET "patb_sw<5>" LOC = "P34";
NET "patb_sw<4>" LOC = "P35";
NET "reset_sw" LOC = "P8";
NET "preset_sw" LOC = "P11";

========================================================*/


module pulse_gen(
	clk,
	range_sw, div_sw, preset_sw, reset_sw, pata_sw, patb_sw,
	n_nck_out, n_pck_out, n_pata, n_patb);

	input			clk;
	input	[2:0]	range_sw;
	input	[1:0]	div_sw;
	input			preset_sw;
	input			reset_sw;
	input	[7:0]	pata_sw;
	input	[7:0]	patb_sw;

	output			n_nck_out, n_pck_out, n_pata, n_patb;

	wire			clk_50n, clk_500n;
	wire			clk_5u, clk_50u, clk_500u, clk_5m, clk_50m, clk_500m;
	wire			div_clk1, div_clk2, div_clk5, div_clk;
	wire	[2:0]	clk_count;
	wire			preset;
	wire			nck_out, pck_out, pata, patb, dpata, dpatb;
 
	assign		clk_50n = clk;
	clk_div10a	clk_div10_1(.clk(clk), .rst(reset_sw), .div_clk(clk_500n));	
	clk_div10a	clk_div10_2(.clk(clk_500n), .rst(reset_sw), .div_clk(clk_5u));	
	clk_div10a	clk_div10_3(.clk(clk_5u), .rst(reset_sw), .div_clk(clk_50u));	
	clk_div10a	clk_div10_4(.clk(clk_50u), .rst(reset_sw), .div_clk(clk_500u));	
	clk_div10a	clk_div10_5(.clk(clk_500u), .rst(reset_sw), .div_clk(clk_5m));	
	clk_div10a	clk_div10_6(.clk(clk_5m), .rst(reset_sw), .div_clk(clk_50m));	
	clk_div10a	clk_div10_7(.clk(clk_50m), .rst(reset_sw), .div_clk(clk_500m));	

	mux8	rangesel(.in({clk_500m, clk_50m, clk_5m, clk_500u, clk_50u, clk_5u,
							clk_500n, clk_50n}),.sel(range_sw), .out(div_clk1) );

	clk_div2a	clk_div2a(.clk(div_clk1), .rst(reset_sw), .div_clk(div_clk2)  );
	clk_div5a	clk_div5a(.clk(div_clk1), .rst(reset_sw), .div_clk(div_clk5)  );

	mux4		divsel(.in({1'b0, div_clk5, div_clk2, div_clk1}), .sel(div_sw),
					.out(div_clk)  );

	assign preset = preset_sw | (div_sw[0] & div_sw[1]);

	clk_div2pn	clk_div2pn(.clk(div_clk), .rst(reset_sw), .pr(preset),
 					.div_clkp(pck_out), .div_clkn(nck_out) );

	counter3	counter31(.clk(div_clk), .rst(reset_sw), .out(clk_count));

	mux8		pata_sel(.in(pata_sw), .sel(clk_count), .out(pata));
	mux8		patb_sel(.in(patb_sw), .sel(clk_count), .out(patb));
	dff			pata_ff(.clk(div_clk), .rst(reset_sw), .d(pata), .q(dpata));
	dff			patb_ff(.clk(div_clk), .rst(reset_sw), .d(patb), .q(dpatb));


	assign		n_pata = ~dpata;
	assign		n_patb = ~dpatb;
	assign		n_pck_out = ~pck_out;
	assign		n_nck_out = ~nck_out;

endmodule


module clk_div10a(
	clk, rst, div_clk
	);

	input	clk, rst;
	output	div_clk;
	reg		[3:0]	cnt;
	reg		div_clk;

	always@(posedge clk or posedge rst) begin
		if(rst) begin
			cnt <= 4'd0;
			div_clk <= 1'b0;
		end
		else begin
			if(cnt == 4'd9) begin
				cnt <= 4'd0;
				div_clk <= 1'b1;
			end
			else begin
				cnt <= cnt + 1;
				div_clk <= 1'b0;
			end
		end
	end
endmodule


module clk_div2a(
	clk, rst, div_clk
	);

	input	clk, rst;
	output	div_clk;
	reg		div_clk;

	always@(posedge clk or posedge rst) begin
		if(rst) begin
			div_clk <= 1'b0;
		end
		else begin
			div_clk <= ~div_clk;
		end
	end
endmodule

module clk_div2pn(
	clk, rst, pr, div_clkp, div_clkn
	);

	input	clk, rst, pr;
	
	output	div_clkp, div_clkn;
	reg		div_clkp, div_clkn;

	always@(posedge clk or posedge rst or posedge pr) begin
		if(rst) begin
			div_clkp <= 1'b0;
			div_clkn <= 1'b1;
		end
		else if(pr) begin
			div_clkp <= 1'b1;
			div_clkn <= 1'b0;
		end
		else begin
			div_clkp <= ~div_clkp;
			div_clkn <= ~div_clkn;
		end
	end
endmodule


module clk_div5a(
	clk, rst, div_clk
	);

	input	clk, rst;
	output	div_clk;
	reg		[2:0]	cnt;
	reg		div_clk;

	always@(posedge clk or posedge rst) begin
		if(rst) begin
			cnt <= 3'd0;
			div_clk <= 1'b0;
		end
		else begin
			if(cnt == 3'd4) begin
				cnt <= 4'd0;
				div_clk <= 1'b1;
			end
			else begin
				cnt <= cnt + 1;
				div_clk <= 1'b0;
			end
		end
	end
endmodule

module mux8(
	in, out, sel
	);

	input	[7:0]	in;
	output			out;
	input	[2:0]	sel;

	assign out = 	(sel == 3'b000) ? in[0] :
					(sel == 3'b001) ? in[1] :
					(sel == 3'b010) ? in[2] :
					(sel == 3'b011) ? in[3] :
					(sel == 3'b100) ? in[4] :
					(sel == 3'b101) ? in[5] :
					(sel == 3'b110) ? in[6] :
					(sel == 3'b111) ? in[7] : 1'bx;
endmodule


module mux4(
	in, out, sel
	);

	input	[3:0]	in;
	output			out;
	input	[1:0]	sel;

	assign out = 	(sel == 2'b00) ? in[0] :
					(sel == 2'b01) ? in[1] :
					(sel == 2'b10) ? in[2] :
					(sel == 2'b11) ? in[3] : 1'bx;
endmodule


module counter3(
	clk, rst, out
	);

	input		clk, rst;
	output	[2:0]	out;
	reg		[2:0]	out;

	always@(posedge clk or posedge rst) begin
		if(rst) begin
			out <= 3'd0;
		end
		else begin
			out <= out + 1;
		end
	end
endmodule


module dff(
	clk, rst, d, q
	);

	input	clk, rst, d;
	output	q;
	reg		q;

	always@(posedge clk or posedge rst) begin
		if(rst) begin
			q <= 1'b0;
		end
		else begin
			q <= d;
		end
	end
endmodule